The present invention relates to a semiconductor memory, and more specifically to a multiport memory provided with a RAM (random access memory) port and a SAM (serial access memory) port.
FIG. 6 shows an essential portion of a prior art multiport memory, which is composed of a RAM port cell array 53 in which dynamic type memory cells are arranged in matrix form; a SAM port data register 51 composed of serial data registers arranged in the column direction and connected to a row wire of the RAM port cell array 53, respectively; and a data transfer gate 52 for transferring data between the RAM port cell array 53 and the SAM port data register 51 in response to a data transfer control signal TRG.
In the multiport memory provided with the RAM port and the SAM port on the same chip as described above, since high speed data access from the SAM port and another access from a CPU to the RAM port without synchronism with the high speed data access are both enabled, a wide application is being expected as image memory, for instance.
In contrast with these excellent performance, however, since the multiport memory is provided with not only all the functions as general purpose dynamic memory but also other special functions, the evaluation and failure analysis of the products are extremely complicated and diversified, thus raising a problem or difficulty when the multiport memory is practically manufactured.
Furthermore, the operational failure analysis related to data transfer between the RAM port and the SAM port is particularly important and complicated in various failure analyses related to the multiport memory. In particular, in the read transfer mode in which data are transferred from the RAM port to the SAM port, it is necessary to switch the operation mode of the SAM port from write cycle mode (serial in) to read cycle mode (serial out), and simultaneously to transfer data stored in any given one-row memory cells of the RAM port to a SAM port data register and further to read a head address (referred to as a TAP address) required to read the data in serial from the RAM port. Since these operations are effected continuously, the analysis to ascertain whether operational failure occurs in the mode switching operation or the data transfer operation becomes extremely complicated.
To explain an example of failure analysis, the SAM port operation in the prior art memory will be described hereinbelow with reference to FIG. 7. The serial data registers of the SAM port register 51 are connected to a data line pair SDQn and SDQn, respectively; and these data line pairs SDQn and SDQn are all connected to a serial input buffer 62. The serial input buffer 62 is provided with a serial input/output terminal SIOn. A serial input control circuit 61 to which a serial clock SC and a serial enable signal SE are inputted is connected to this serial input buffer 62.
When a serial enable signal SE is inputted to the serial input control circuit 61, since the serial input buffer 62 is activated, serial data are inputted therein or outputted therefrom through the serial data input/output terminal SIOn on the basis of timing of the serial clock SC.
Here, where data in the SAM port are read to outside, first it is necessary to switch the operation mode of the SAM port from the write cycle mode to the read cycle mode. In this switching operation, however, since data must be transferred from the RAM port to the SAM port, this switching operation ends after the data transfer operation has been completed. Therefore, data stored in the SAM port cannot be read to outside before the operation mode has been switched, and additionally data stored in the data register 51 before the mode is switched are destructed by this data transfer. Therefore, data stored in the RAM port cell array 53 must be once transferred to the SAM port data register 51, and these transferred data must be read. Here, in case the read data are erroneous, it has been extremely difficult to conduct failure analysis by separating the problem caused when data are transferred to the SAM port from that caused when the transferred data are read to outside.
As described above, in the prior-art multiport memory, there exist problems in that the operational failure in the read transfer mode is difficult to analyze; it takes much time to identify the defective location; a long turnaround time (TAT) is required to refine the memory into practical products where the operational failure is overlooked.